SoC Architect

Key Responsibilities

• System Design & Integration: Define the high‑level architecture of the SoC and determine which components will be included on the chip.
• Collaborate with hardware design teams to guide the implementation of the chip’s physical design.
• Coordinate with our firmware & GNSS team to ensure the SoC architecture supports efficient execution of software, including drivers, operating systems and applications.
• Define and implement security features to protect the SoC from vulnerabilities.
• Keep up with advances in the semiconductor industry to ensure the SoC architecture remains scalable and adaptable for future generations of products.
• Manage product timelines and deliverables, ensuring the SoC development follows the planned schedule and stays within budget.

Requirements

Qualinx is looking for a result‑driven and conscientious senior SoC Architect. The ideal candidate must have:

• Minimum of 12 years experience in RTL Design, RTL Verification, CPU‑based Chip/Components Concepts and Architecture.
• Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, Flash, NVMe…).
• At least 10 years’ experience with the Digital ASIC Flows, RTL design, Design Verification, Debug and Trace methodologies, Test (e.g., DFT, JTAG, Scan, BIST).
• Solid understanding of chip packaging.
• Proficiency in hardware‑software interface design, including device drivers, firmware, and low‑level software optimizations.
• Strong problem‑solving skills to troubleshoot and resolve architectural issues related to SoC integration, performance, and power efficiency.
• Experience with silicon bring‑up, validation, and post‑silicon debug methodologies.
• Practical experience with IP integration, including integration flows, interconnect design (e.g., AMBA, AXI, AHB), and managing key IP integration architecture tasks.
• Deep understanding of peripherals, Pin Function Assignment, and multiplexing, as well as familiarity with various communication protocols (e.g. MIPI, LVDS, SPI, I2C, UART).
• Experience in analog‑digital interface design, including RF and Analog components like PLL, ADC, DAC, LNA, PA, DCDC, LDO… integration, and layout constraints for minimizing noise and signal interference.
• Knowledge of low‑power design techniques, including clock gating, power gating, and multi‑voltage domains (UPF/CPF).
• Deep understanding of library selection and design, with a focus on leakage power‑aware methodologies to optimize performance and power trade‑offs.
• Hands‑on experience with IP selection to meet the specific needs of the design.
• Strong experience in selecting appropriate I/O technologies and designing for signal integrity, noise resilience, and power efficiency.
• Strong knowledge of pad ring placement and ESD strategy.
• In‑depth expertise in clock and reset architecture design, including low‑jitter clock distribution networks, clock domain crossing issues, and reset synchronization.
• Solid understanding of power management units and implementing various power sequencing schemes, including wake, sleep, and deep sleep modes for power efficiency.
• Solid knowledge in signal processing, communication system.
• Exposure to all aspects of RFIC system design.

What's in it for you?

• Ownership and Impact: Employee equity to share in the success you help create.
• Well‑being Matters: Access to wellness resources, including company discounts and a free mental healthcare platform.
• Global Talent, Local Support: Full support throughout the visa process for relocating team members.
• Future‑Focused Benefits: Pension savings contribution to help you plan ahead with confidence.
• Inspiring Workspace: Modern, vibrant office equipped to help you do your best work.
• Scale‑up Team Spirit: Celebrating wins together with quarterly events, games, and unforgettable experiences.