SoC Architect

Key ResponsibilitiesulliSystem Design Integration: Define the high‑level architecture of the SoC and determine which components will be included on the chip. /liliCollaborate with hardware design teams to guide the implementation of the chip’s physical design. /liliCoordinate with our firmware GNSS team to ensure the SoC architecture supports efficient execution of software, including drivers, operating systems and applications. /liliDefine and implement security features to protect the SoC from vulnerabilities. /liliKeep up with advances in the semiconductor industry to ensure the SoC architecture remains scalable and adaptable for future generations of products. /liliManage product timelines and deliverables, ensuring the SoC development follows the planned schedule and stays within budget. /li /ulRequirementspQualinx is looking for a result‑driven and conscientious senior SoC Architect. The ideal candidate must have: /pulliMinimum of 12 years experience in RTL Design, RTL Verification, CPU‑based Chip/Components Concepts and Architecture. /liliDeep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, Flash, NVMe…). /liliAt least 10 years’ experience with the Digital ASIC Flows, RTL design, Design Verification, Debug and Trace methodologies, Test (e.g., DFT, JTAG, Scan, BIST). /liliSolid understanding of chip packaging. /liliProficiency in hardware‑software interface design, including device drivers, firmware, and low‑level software optimizations. /liliStrong problem‑solving skills to troubleshoot and resolve architectural issues related to SoC integration, performance, and power efficiency. /liliExperience with silicon bring‑up, validation, and post‑silicon debug methodologies. /liliPractical experience with IP integration, including integration flows, interconnect design (e.g., AMBA, AXI, AHB), and managing key IP integration architecture tasks. /liliDeep understanding of peripherals, Pin Function Assignment, and multiplexing, as well as familiarity with various communication protocols (e.g. MIPI, LVDS, SPI, I2C, UART). /liliExperience in analog‑digital interface design, including RF and Analog components like PLL, ADC, DAC, LNA, PA, DCDC, LDO… integration, and layout constraints for minimizing noise and signal interference. /liliKnowledge of low‑power design techniques, including clock gating, power gating, and multi‑voltage domains (UPF/CPF). /liliDeep understanding of library selection and design, with a focus on leakage power‑aware methodologies to optimize performance and power trade‑offs. /liliHands‑on experience with IP selection to meet the specific needs of the design. /liliStrong experience in selecting appropriate I/O technologies and designing for signal integrity, noise resilience, and power efficiency. /liliStrong knowledge of pad ring placement and ESD strategy. /liliIn‑depth expertise in clock and reset architecture design, including low‑jitter clock distribution networks, clock domain crossing issues, and reset synchronization. /liliSolid understanding of power management units and implementing various power sequencing schemes, including wake, sleep, and deep sleep modes for power efficiency. /liliSolid knowledge in signal processing, communication system. /liliExposure to all aspects of RFIC system design. /li /ulWhat's in it for you?ulliOwnership and Impact: Employee equity to share in the success you help create. /liliWell‑being Matters: Access to wellness resources, including company discounts and a free mental healthcare platform. /liliGlobal Talent, Local Support: Full support throughout the visa process for relocating team members. /liliFuture‑Focused Benefits: Pension savings contribution to help you plan ahead with confidence. /liliInspiring Workspace: Modern, vibrant office equipped to help you do your best work. xgiwjmb /liliScale‑up Team Spirit: Celebrating wins together with quarterly events, games, and unforgettable experiences. /li /ulbr