Senior Layout Design Engineer — Lead Analog/CMOS Layout
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A leading technology firm in the Netherlands is seeking a Sr. Layout Design Engineer responsible for top-level chip planning and custom layouts for CMOS and BiCMOS circuits. The ideal candidate will have at least 10 years of experience in layout design, strong skills in Cadence Virtuoso, and a solid understanding of layout challenges including parasitics and signal integrity. The role demands attention to detail and collaborative skills in a fast-paced environment.br#J-18808-Ljbffr
Vacature geplaatst op 2 dagen geleden
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